1. Technical Field
The invention relates to a ferroelectric memory device that stores data according to polarization states of a ferroelectric capacitor, a method for driving the same, and electronic apparatuses.
2. Related Art
In a ferroelectric memory device that stores data using the hysteresis characteristic of its ferroelectric capacitor, a readout voltage is applied to the plate line, and a potential on the bit line which elevates according to the amount of charge discharged from the ferroelectric capacitor and a reference potential are compared to each other, whereby data is judged. In this instance, the voltage applied to the plate line is voltage-divided by the capacitance of the ferroelectric capacitor and the parasitic capacitance. For this reason, the readout voltage applied to the ferroelectric capacitor becomes smaller than the readout voltage applied to the plate line. There is a trend to set the power supply voltage lower because of the demand for a reduction in the power consumption of electronic apparatuses. When the power supply voltage is low, the amount of readout charge discharged onto the bit line from the ferroelectric, capacitor becomes smaller, and the readout margin lowers. To solve such a problem, a bit line sensing method has been proposed in which the initial potential on the bit line is controlled to be at a ground potential, and the readout voltage to be applied to the plate line is applied generally as it is to the ferroelectric capacitor thereby increasing the readout margin. For example, as a patent document describing the bit line ground sensing method, Japanese laid-open patent application JP-A-2002-133857 may be relevant.
According to an ordinary bit line ground sensing method, when the ferroelectric capacitance of “0” data is Cf0, the ferroelectric capacitance of “1” data is Cf1, the capacitance of a node to which charge on the bit line is transferred (hereafter, referred to as a data line) is Ctank, the initial potential on the data line is −Vini, the power source potential is VCC, the potential on the data line when “0” data is read out is Vtank0, and the potential on the data line when “1” is readout is Vtank1, the following relation is established.Vtank0=−Vini+VCC×Cf0/CtankVtank1=−Vini+VCC×Cf1/Ctank
This relation indicates that, the smaller the capacitance Ctank of the data line, the greater the potential difference between the potential on the data line when “0” data is read out and the potential on the data line when “1” data is read out (hereafter referred to as the readout margin), whereby the readout accuracy can be improved.
However, because the potential on the data line would not become greater than the initial potential (ground potential) on the bit line, neither “VCC×Cf0/Ctank” or “VCC×Cf1/Ctank” would become greater than Vini. Therefore, the formula shown above can be expressed by a formula below. It is noted that, in the following formula, a function min is a function with a return value that is the smallest parameter among plural parameters.Vtank0=min(VCC×Cf0/Ctank,Vini)−Vini Vtank1=min(VCC×Cf1/Ctank,Vini)−Vini 
The readout margin ΔV can be obtained as follows.ΔV=Vtank1−Vtank0=min(VCC×Cf1/Ctank,Vini)−min(VCC×Cf0/Ctank,Vini)
According to the above formula, the readout margin ΔV assumes a maximum value at a point where Vtank1=0. The value of Ctank and the readout margin ΔVmax at this moment are as follows.Ctank=Cf1×VCC/Vini ΔVmax=Vini(1−Cf0/Cf1)
In theory, readout margins greater than ΔVmax cannot be obtained by the bit line ground sensing method described above. For example, when Cf0/Cf1=1/3, ΔVmax=2*Vini/3. The design value of Ctank has an optimum value, and the readout margin would reduce when its value is either greater or smaller.